1) BGA (Ball Grid Array)
BGA is one of the surface mount packages, and it has an array of spherical contacts. Spherical bumps are made on the back of the printed circuit board in a display mode to replace the pins. The LSI chip is assembled on the front side of the printed circuit board and then sealed by molding resin or potting. Pins can exceed 200, which is for a multi-pin LSI package.
The package body can also be made smaller than QFP(Quad Flat Package). For example, with a pin center distance of 1.5mm, a 360- pin BGA is only 31 square millimeters. On the other hand, with a pin center distance of 0.5mm, a 304-pin QFP is 40 square millimeters. Moreover, BGA does not have to worry about QFP pin deformation issues.
Motorola Corporation of the United States developed this package. It was first adopted in portable phones and other devices and may be popularized in personal computers in the United States in the future. Initially, the BGA pin (bump) center distance was 1.5mm, and the total number of pins was 225. There are also some LSI manufacturers that are developing 500-pin BGAs.
The problem with BGA is the visual inspection after reflow soldering. It is not yet clear whether an effective visual inspection method is available. Some believe that due to the large center distance of welding, the connection can be regarded as stable and can only be processed through functional inspection.
American Motorola Company calls the package sealed with molded resin as OMPAC, and the package sealed with potting method is called GPAC (see OMPAC and GPAC).
2) BQFP (Bumpered Quad Flat Package)
It is one of the QFP packages with protrusions (buffer pads) that are provided at the four corners of the package body to prevent bending and deformation of the pins during transportation. American semiconductor manufacturers mainly use this package in ASICs such as microprocessors and circuits. The pin center distance is about 0.635mm, and the pin number ranges from 84 to 196. (see QFP).
3) Butt Welding PGA(Butt Joint Pin Grid Array)
It is another name for Surface mount BGA (see surface mount BGA).
4) C-(ceramic)
It indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.
5) Cerdip
Ceramic dual in-line package, sealed with glass, is used for ECL RAM, DSP (digital signal processor), and other circuits. With glass windows, Cerdip is used for ultraviolet erasable EPROM. The pin center distance is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is expressed as DIP-G (G means glass seal).
6) Cerquad
It is one of the surface mount packages. The ceramic sealed QFP is used for packaging DSP logic under the seal, such as LSI circuits. With windows, Cerquad is used to encapsulate EPROM circuits. The heat dissipation is better than that of plastic QFP, and it can tolerate under natural air-cooling conditions of 1.5 to 2W of power. However, packaging costs three to five times higher than plastic QFP. The center distance between pins has a variety of specifications, such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, and so on. The number of pins ranges from 32 to 368.
7) CLCC (Ceramic Leaded Chip Carrier)
It is one of the surface mount packages that is a ceramic chip carrier with pins. The pins are drawn from the four sides of the package and are in a T-shape. With windows, it is used to package ultraviolet erasable EPROM and EEPROM microcomputer circuits. This package is also called QFJ, QFJ-G (see QFJ).
8) COB (Chip on Board)
Chip packaging is one of the bare chip mounting technologies. The semiconductor chip is handed over and mounted on the printed circuit board. The electrical connection between the chip and the substrate is made by wire stitching. The electrical connection between the chip and the substrate is covered with resin to ensure reliability. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip bonding technology.
9) DFP (Dual Flat Package)
Dual Flat Package is another name for SOP (see SOP). This term was common, but it is not used now.
10) DIC (Dual in-line Ceramic Package)
It is another name for ceramic DIP (including glass seal) (see DIP).
11) DIL (Dual in-line)
It is another name for DIP (see DIP). European semiconductor manufacturers often use this name.
12) DIP (dual in-line package)
Dual in-line Package is one of the plug-in packages. The pins are drawn from both sides of the package, and the package materials are plastic and ceramic.
DIP is the most popular plug-in package, and its application range includes standard logic ICs, memory LSIs, and microcomputer circuits. The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow DIP), respectively. But in most cases, no distinction is made, and they are simply collectively referred to as DIP. In addition, ceramic DIP sealed with low-melting glass is also called Cerdip (see Cerdip).
13) DSO (Dual Small Out-line)
Dual Small Out-line package is another name for SOP (see SOP). Some semiconductor manufacturers use this name.
14) DICP (Dual Tape Carrier Package)
Dual Tape Carrier Package is one of TCP (carrying package). The pins are made on the insulating tape and lead out from both sides of the package. Due to the use of TAB (Automatic On-Load Soldering) technology, the package outline is very thin. It is often used in LCD driver LSI, but most of them are customized products. In addition, the 0.5mm thick memory LSI book package is in the development stage. In Japan, in accordance with the EIAJ (Electronic Industries Association of Japan) standards, DICP is named DTP.
15) DTP (Dual Tape Carrier Package)
It is the same as above DICP. The Electronic Industries Association of Japan names it DTP.
16) FP (Flat Package)
Flat Package is one of the surface mount packages. It is another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
17) Chip
Flip-chip welding is one of the bare chip packaging technologies to make metal bumps in the electrode area of the LSI chip and then connect the metal bumps with the electrode area on the printed circuit board.
The footprint of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction will occur at the joint, which will affect the reliability of the connection. Therefore, it is necessary to use resin to reinforce the LSI chip and use a substrate material with substantially the same thermal expansion coefficient.
18) FQFP (Fine Pitch Quad Flat Package)
FQFP usually refers to the QFP with a lead center distance less than 0.65mm (see QFP). Some conductor manufacturers use this name.
19) CPAC (Globe Top Pad Array Carrier)
American Motorola Company’s nickname for BGA (see BGA).
20) CQFP (Quad Flat Package with Guard Ring)
It is a four-side pin flat package with a guard ring. It is one of the plastic QFPs in which the pins are masked with a resin protection ring to prevent bending and deformation. Before assembling the LSI on the printed circuit board, cut the lead from the guard ring and make it into a seagull wing shape (L shape). This kind of package has been mass-produced by Motorola Company in the United States. The pin center distance is 0.5mm, and the number of pins is about 208 at most.
21) H- (With Heat Sink)
It means a radiator. For example, HSOP means SOP with a heat sink.
22) Pin Grid Array (Surface Mount Type)
Usually, PGA is a plug-in package with a pin length of about 3.4mm. The surface mount PGA has display-like pins on the bottom surface of the package, and its length ranges from 1.5mm to 2.0mm. Mounting uses the method of butt welding with the printed circuit board, so it is also called butt welding PGA. Because the pin center distance is only 1.27mm, which is half smaller than the plug-in type PGA, the package body cannot be made so large. The number of pins is more than that of the plug-in type (250～528), which is a package for large-scale logic LSIs. The encapsulated substrates include multilayer ceramic substrates and glass epoxy resin printing bases. The packaging of multilayer ceramic substrates has been put into practical use.
23) JLCC (J-leaded chip carrier) J-leaded Chip Carrier
It is another name for CLCC with window and ceramic QFJ with window (see CLCC and QFJ). Some semiconductor manufacturers adopted the name.
24) LCC (Leadless Chip Carrier)
Leadless Chip Carrier refers to a surface-mount package in which the four sides of the ceramic substrate are only in contact with electrodes without leads. It is an IC package for high-speed and high-frequency, also called ceramic QFN or QFN-C (see QFN).
25) LGA (Land Grid Array)
Contact Display Package is a package with array state electrode contacts that are made on the bottom surface. Just plug in the socket when assembling. There are now practical ceramic LGAs with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance), which are used in high-speed logic LSI circuits.
Compared with QFP, LGA can accommodate more input and output pins in a smaller package. In addition, since the impedance of the lead is small, it is very suitable for high-speed LSI. However, due to the complicated production and high cost of sockets, they are basically not used much now. It is expected that its demand will increase in the future.
26) LOC (Lead on Chip)
Chip Lead Package is one of the LSI packaging technologies. It has a structure in which the front end of the lead frame is above the chip, bump solder joints are made near the center of the chip, and wire stitching is used for electrical connection. Compared with the original structure in which the lead frame is arranged near the side of the chip, the chip is contained in the same size package and has a width of about 1 mm.
27) LQFP (Low Profile Quad Flat Package)
Thin QFP refers to the QFP with a package body thickness of 1.4mm. It is the name used by the Japanese Electronic Machinery Industry according to the new form factor formulated QFP.
28) One of L-QUAD
Aluminum nitride is used for packaging substrates that have a thermal conductivity 7-8 times higher than aluminum oxide and have better heat dissipation. The frame of the package is aluminum oxide, and the chip is sealed by potting, thereby suppressing the cost. It is a package developed for logic LSI, which can tolerate W3 power under natural air-cooling conditions. 208-pin (0.5mm center distance) and 160-pin (0.65mm center distance) LSI logic packages have been developed, and mass production began in October 1993.
29) MCM (multi module)
It is a package in which multiple semiconductor bare chips are assembled on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C, and MCM-D.
MCM-L is a component using a common glass epoxy multilayer printed circuit board. The wiring density is not very high, and the cost is low. MCM-C uses thick film technology to form multilayer wiring and uses ceramic (alumina or glass-ceramic) as a substrate component, which is similar to a thick film hybrid IC using a multilayer ceramic substrate. There is no obvious difference between the two. The wiring density is higher than MCM-L. MCM-D uses thin-film technology to form multilayer wiring, with ceramic (aluminum oxide or aluminum nitride) of Si or Al as the substrate component. The wiring scheme is the highest among the three components, but the cost is also high.
30) MFP ( Mini Flat Package)
It is another name for plastic SOP or SSOP (see SOP and SSOP). It is the name adopted by some semiconductor manufacturers.
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